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	\| 2004 \|\| [[Pentium4#Prescott\|Pentium 4]] (Prescott)<br/>[[Celeron D]], [[Pentium D]] (2005) \|\|rowspan="2" colspan="3" style="background: #ececec;" \| 36-bit \|\| [[EM64T]] (enabled on selected models of Pentium 4 and Celeron D), [[SSE3]], 2nd gen. NetBurst pipelining, dual-core (on-die: Pentium D 8xx, on-chip: Pentium D 9xx), [[Intel VT]](Pentium 4 6x2), socket [[LGA 775]]		\| 2004 \|\| [[Pentium4#Prescott\|Pentium 4]] (Prescott)<br/>[[Celeron D]], [[Pentium D]] (2005) \|\|rowspan="2" colspan="3" style="background: #ececec;" \| 36-bit \|\| [[EM64T]] (enabled on selected models of Pentium 4 and Celeron D), [[SSE3]], 2nd gen. NetBurst pipelining, dual-core (on-die: Pentium D 8xx, on-chip: Pentium D 9xx), [[Intel VT]](Pentium 4 6x2), socket [[LGA 775]]
	\|-		\|-
	\| 2006 \|\| [[Intel Core 2]] <br/>[[Pentium Dual-Core]] (2007)<br/> [[Celeron Dual-Core]] (2008) \|\|[[Intel 64]] (<<== EM64T), [[SSSE3]](65nm), wide dynamic execution, µ-op fusion, macro-op fusion in 16-bit and 32-bit mode,<ref name="intel-optimization-for-macro-fusion">{{~~cite web~~\|url=https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf\|title=Intel 64 and IA-32 Architectures Optimization Reference Manual\|at=3.4.2.2 Optimizing for Macro-fusion\|date=September 2019\|publisher=Intel}}</ref><ref name="agner-fog-microarchitecture">{{~~cite web~~\|url=https://www.agner.org/optimize/microarchitecture.pdf\|title=The microarchitecture of Intel, AMD and VIA CPUs\|last=Fog\|first=Agner\|page=107\|quote=Core2 can do macro-op fusion only in 16-bit and 32-bit mode. Core Nehalem can also do this in 64-bit mode.}}</ref> on-chip quad-core(Core 2 Quad), Smart Shared L2 Cache (Intel Core 2 "Merom")		\| 2006 \|\| [[Intel Core 2]] <br/>[[Pentium Dual-Core]] (2007)<br/> [[Celeron Dual-Core]] (2008) \|\|[[Intel 64]] (<<== EM64T), [[SSSE3]](65nm), wide dynamic execution, µ-op fusion, macro-op fusion in 16-bit and 32-bit mode,<ref name="intel-optimization-for-macro-fusion">{{Citiranje weba\|url=https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf\|title=Intel 64 and IA-32 Architectures Optimization Reference Manual\|at=3.4.2.2 Optimizing for Macro-fusion\|date=September 2019\|publisher=Intel}}</ref><ref name="agner-fog-microarchitecture">{{Citiranje weba\|url=https://www.agner.org/optimize/microarchitecture.pdf\|title=The microarchitecture of Intel, AMD and VIA CPUs\|last=Fog\|first=Agner\|page=107\|quote=Core2 can do macro-op fusion only in 16-bit and 32-bit mode. Core Nehalem can also do this in 64-bit mode.}}</ref> on-chip quad-core(Core 2 Quad), Smart Shared L2 Cache (Intel Core 2 "Merom")
	\|-		\|-
	\| 2007 \|\| [[AMD Phenom]]/[[AMD Phenom II\|II]](2008)<br/>[[AMD Athlon II\|Athlon II]](2009), [[Turion II]](2009)\|\| colspan="3" style="background: #ececec;" \| 48-bit \|\| Monolithic quad-core(X4)/triple-core(X3), [[SSE4a]], [[Rapid Virtualization Indexing]] (RVI), HyperTransport 3, [[AM2+]] or [[AM3]]		\| 2007 \|\| [[AMD Phenom]]/[[AMD Phenom II\|II]](2008)<br/>[[AMD Athlon II\|Athlon II]](2009), [[Turion II]](2009)\|\| colspan="3" style="background: #ececec;" \| 48-bit \|\| Monolithic quad-core(X4)/triple-core(X3), [[SSE4a]], [[Rapid Virtualization Indexing]] (RVI), HyperTransport 3, [[AM2+]] or [[AM3]]

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2021-12-10T21:14:11Z

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{{mrva}}
'''x86''' ime je obitelj mikroobradnika koji rabe određnu arhitekturu naredbenog skupa, koji je prvotno bio razvijen za mikroobradnik [[Intel 8086]] i [[Intel 8088]] od strane tvrtke Intel. Inače, Intel nije jedina tvrtka koja je doprinjela razvoju x86 arhitekture jer tvrtke kao AMD i VIA Technologies su u mnogome doprinjele razvoju x86 arhitekture.

==Povijest==

Pojam x86 u 1980s i u ranim 1990s, označavao je sve mikroobradnike koji su bili kompatibilini s 16-bitnim [[Intel 8086]]. Pojam x86 danas se rabi za mikroobradnike koji su binarno sukladni s 32-bitnim naredbenim skupom koji se prvotono pojavio s mikroobradnikom [[Intel 80386]] 1985. godine. AMD je između 1999. i 2003. godine proširio naredbenu arhitekturu x86 sa 32 na 64-bita, i ova proširna arhitektura dobila je naziv x86-64 dok u kasnijim dokumentima ovo je dobilo naziv [[AMD64]]. Ovu proširenu arhitekturu je usvojila i tvrtka Intel za svoje proizvode, i u svojoj tehničkoj dokumentaciji Intel je ovo prvo referiralo pod nazivom IA32e, potom EM64T, da bi na kraju usvojili Intel 64. Microsoft i Sun Microsystems za ovu arhitekturu rabile su naziv x64, dok su pojedine Linux distributije i BSD rabile naziv AMD64. U svoj operacijskom sustavu Windows, tvrtka Microsoft rabi naziv x86 za 32-bitnu inačicu, dok za 64-bitnu rabi x64.

===Vremenska crta ===

{| class="wikitable" style="text-align: center;font-size: 84%"
|+ Vremnenska crta za mikroobradnike iz porodice x86
|-
! colspan="2" rowspan="2" | Generacija
! rowspan="2" | Opaska
! rowspan="2" | Istaknutiji modeli
! colspan="3" | [[Addresni prostor]]
! rowspan="2" | Istaknute značajke
|-
![[Linearni addresni prostor|Linearni]]
![[Virtualni addresni prostor|Virtualni]]
![[Fizički adresni prostor|Fizički]]
|-
| rowspan="16"|x86 ||rowspan="2" | '''1.''' || 1978. || [[Intel 8086]], [[Intel 8088]](1979) || rowspan="3" style="background: #FAECC8;" | 16-bitni ||rowspan="2" style="background: #FAECC8;" | NA ||rowspan="2" style="background: #FAECC8;" | 20-bitni ||[[16-bitni]] [[arhitektura naredbenog skupa|ISA]], [[IBM PC]] (8088), [[IBM PC/XT]] (8088)
|-
| rowspan="2" | 1982. || [[Intel 80186]], [[Intel 80188]] [[NEC V20]]/V30(1983) || 8086-2 ISA, ugrađeni (80186/80188)
|-
| '''2.''' || [[Intel 80286]] i kolonovi || style="background: #FAECC8;" | 30-bitni ||style="background: #FAECC8;" | 24-bit|| [[zaštićeni mod]], [[IBM PC XT|IBM PC XT 286]], [[IBM PC AT]]
|-
| '''3.''' ([[IA-32]]) || 1985 || [[Intel 80386]], [[AMD Am386]] (1991) || rowspan="13" style="background: #CEE0F2;" | 32-bit || rowspan="13" style="background: #CEE0F2;" | 46-bitni ||rowspan="5" style="background: #CEE0F2;" | 32-bitni || [[32-bitni]] [[arhitektura naredbenog skupa|ISA]], [[straničenje]], [[IBM PS/2]]
|-
| '''4.''' (protočnjak, priručna memorija) || 1989 || [[Intel 80486]] [[Cyrix]] Cx486[[Cyrix Cx486SLC|S]]/[[Cyrix Cx486DLC|D]]LC(1992) [[AMD Am486]](1993.)/[[AMD Am5x86|Am5x86]](1995) || [[pipelining]], on-die [[x87]] [[Jedinica za pomični zarez|FPU]] (486DX), on-die [[CPU priručna memorija|priručna memorija]]
|-
| rowspan="3" | '''5.''' ([[Superscalar]]) || 1993 || Intel [[P5 (microarchitecture)|Pentium]], [[Pentium MMX]](1996) || [[Superscalar]], [[64-bit]] [[sabirnica]], brži FPU, [[MMX (naredbeni skup)|MMX]] (Pentium MMX), [[Advanced Programmable Interrupt Controller|APIC]], [[Simetrično multiprocesiranje |SMP]]
|-
| 1994. || [[NexGen]] [[NexGen Nx586|Nx586]] AMD [[AMD K5|5k86]]/[[AMD K5|K5]] (1996) || Diskretna multiarhitektura (µ-op prevođenje)
|-
| 1995. || [[Cyrix Cx5x86]] [[Cyrix 6x86]]/MX(1997.)/[[Cyrix MII|MII]](1998.) || [[dinamično izvršavanje]]
|-
| rowspan="3" | '''6.''' ([[Physical Address Extension|PAE]], µ-op prevođenje)|| 1995. || Intel [[Pentium Pro]] || rowspan="2" style="background: #CEE0F2;" | 36-bitni ([[Proširena fizička adresa|PAE]])|| µ-op prevođenje, naredba za uvjetno pomicanje, [[dinamički izvršavanje]], [[spekulativno izvršavanje]], trostrani superskalarni x86, superskalarni FPU, [[Proširena fizička adresa]], ugrađena [[L2 priručna memorija]]
|-
| 1997. ||Intel [[Pentium II]], [[Pentium III]] (1999.) [[Celeron]](1998.), [[Xeon]](1998.) || on-package (Pentium II) or on-die (Celeron) L2 priručna memorija, [[Streaming SIMD Extensions|SSE]] (Pentium III), [[SLOT 1]], [[Socket 370]] ili [[SLOT 2]] (Xeon)
|-
| 1997. || [[AMD K6]]/[[AMD K6-2|K6-2]](1998.)/[[AMD K6-III|K6-III]](1999.)|| style="background: #CEE0F2;" | 32-bitni ||[[3DNow!]], troslojna priručna memorija (K6-III)
|-
| rowspan="5" | Enhanced Platform|| 1999. || AMD [[Athlon]], [[Athlon XP]]/[[Athlon MP|MP]](2001.) [[Duron]](2000.), [[Sempron]](2004.) || style="background: #CEE0F2;" | 36-bitni || MMX+, 3DNow!+, dvoprotočne sabirnice, [[Slot A]] ili [[Socket A]]
|-
| rowspan = "2" | 2000. || [[Transmeta Crusoe]] || style="background: #CEE0F2;" | 32-bitni || [[Code Morphing Software|CMS]] pogonjen s procesorom na bazi x86, [[Veoma dugačka naredbena riječ|VLIW]]-128 core, on-die memory controller, on-die PCI bridge logic
|-
|Intel [[Pentium 4]] || rowspan="3" style="background: #CEE0F2;" | 36-bitni || [[SSE2]], [[Hyper-Threading|HTT]] (Northwood), NetBurst, quad-pumped bus, Trace Cache, [[Socket 478]]
|-
| rowspan="2" | 2003. || Intel [[Pentium M]] [[Intel Core#Enhanced Pentium M|Intel Core]] (2006.), [[Pentium Dual-Core]] (2007) || [[Micro-op fusion|µ-op fusion]], [[XD bit]] (Dothan) (Intel Core "Yonah")
|-
|[[Transmeta Efficeon]] || [[Code Morphing Software|CMS]] 6.0.4, [[Very long instruction word|VLIW]]-256, [[NX bit]], [[Hyper Transport|HT]]
|-
|style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;" |[[IA-64]]||style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;" |Prijelaz na 64-bitnu arhitekturu 1999 ~ 2005 || 2001 || Intel [[Itanium]] (2001 ~ 2017) || colspan="3" style="background: #ececec;" | 52-bitni || 64-bitna [[Explicitly parallel instruction computing|EPIC]] arhitektura, 128-bit VLIW instruction bundle, on-die hardware IA-32 H/W enabling x86 OSes & x86 applications (early generations), software IA-32 EL enabling x86 applications (Itanium 2), Itanium register files are remapped to x86 registers
|-
| rowspan="25" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;"| [[x86-64]] ||rowspan="25" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;"|Prošireni 64-bitni od 2001. || colspan="6" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;" | x86-64 is the 64-bit extended architecture of x86, its Legacy Mode preserves the entire and unaltered x86 architecture. The native architecture of x86-64 processors, residing in the 64-bit Mode, lacks of access mode in segmentation, presenting 64-bit architectural-permit linear address space, currently, only 48-bit of which is implemented; an adapted IA-32 architecture residing in the Compatibility Mode alongside 64-bit Mode is provided to support most x86 applications
|-
| 2003 || [[Athlon 64]]/[[Athlon 64 FX|FX]]/[[Athlon 64 X2|X2]](2005), [[Opteron]] [[Sempron]](2004)/[[Sempron X2|X2]](2008) [[Turion 64]](2005)/[[Turion 64 X2|X2]](2006) || colspan="3" style="background: #ececec;" | 40-bit || [[AMD64]] (except some Sempron processors presented as purely x86 processors), on-die memory controller, [[HyperTransport]], on-die dual-core (X2), [[AMD-V]] (Athlon 64 Orleans), [[Socket 754]]/[[Socket 939|939]]/[[Socket 940|940]] or [[Socket AM2|AM2]]
|-
| 2004 || [[Pentium4#Prescott|Pentium 4]] (Prescott) [[Celeron D]], [[Pentium D]] (2005) ||rowspan="2" colspan="3" style="background: #ececec;" | 36-bit || [[EM64T]] (enabled on selected models of Pentium 4 and Celeron D), [[SSE3]], 2nd gen. NetBurst pipelining, dual-core (on-die: Pentium D 8xx, on-chip: Pentium D 9xx), [[Intel VT]](Pentium 4 6x2), socket [[LGA 775]]
|-
| 2006 || [[Intel Core 2]] [[Pentium Dual-Core]] (2007) [[Celeron Dual-Core]] (2008) ||[[Intel 64]] (<<== EM64T), [[SSSE3]](65nm), wide dynamic execution, µ-op fusion, macro-op fusion in 16-bit and 32-bit mode,<ref name="intel-optimization-for-macro-fusion">{{cite web|url=https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf|title=Intel 64 and IA-32 Architectures Optimization Reference Manual|at=3.4.2.2 Optimizing for Macro-fusion|date=September 2019|publisher=Intel}}</ref><ref name="agner-fog-microarchitecture">{{cite web|url=https://www.agner.org/optimize/microarchitecture.pdf|title=The microarchitecture of Intel, AMD and VIA CPUs|last=Fog|first=Agner|page=107|quote=Core2 can do macro-op fusion only in 16-bit and 32-bit mode. Core Nehalem can also do this in 64-bit mode.}}</ref> on-chip quad-core(Core 2 Quad), Smart Shared L2 Cache (Intel Core 2 "Merom")
|-
| 2007 || [[AMD Phenom]]/[[AMD Phenom II|II]](2008) [[AMD Athlon II|Athlon II]](2009), [[Turion II]](2009)|| colspan="3" style="background: #ececec;" | 48-bit || Monolithic quad-core(X4)/triple-core(X3), [[SSE4a]], [[Rapid Virtualization Indexing]] (RVI), HyperTransport 3, [[AM2+]] or [[AM3]]
|-
| rowspan="4" | 2008 || [[Intel Core 2]] (45nm) ||rowspan = "4" colspan="3" style="background: #ececec;" | 40-bit || [[SSE4.1]]
|-
| [[Intel Atom]] || netbook or low power smart device processor, P54C core reused
|-
| Intel [[Core i7]] [[Core i5]] (2009), [[Intel Core i3|Core i3]] (2010)|| QuickPath, on-chip GMCH ([[Clarkdale (microprocessor)|Clarkdale]]), [[SSE4|SSE4.2]], [[Second Level Address Translation#Extended Page Tables|Extended Page Tables]] (EPT) for virtualization, macro-op fusion in 64-bit mode,<ref name="intel-optimization-for-macro-fusion"/><ref name="agner-fog-microarchitecture"/> (Intel Xeon "Bloomfield" with Nehalem microarchitecture)

|-
| [[VIA Nano]] || [[hardware-based encryption]]; adaptive [[power management]]
|-
| 2010 ||[[Bulldozer (microarchitecture)| AMD FX]] || colspan="3" style="background: #ececec;" | 48-bit || octa-core, CMT(Clustered Multi-Thread), FMA, OpenCL, AM3+
|-
| rowspan="3" | 2011 || AMD APU A and E Series ([[AMD Fusion|Llano]]) || colspan="3" style="background: #ececec;" | 40-bit || on-die GPGPU, PCI Express 2.0, [[Socket FM1]]
|-
| AMD APU C, E and Z Series ([[Bobcat (processor)|Bobcat]]) || rowspan = "2" colspan="3" style="background: #ececec;" | 36-bit || low power smart device APU
|-
| [[Intel Core i3]], [[Core i5]] and [[Core i7]] ([[Sandy Bridge (microarchitecture)|Sandy Bridge]]/[[Ivy Bridge (microarchitecture)|Ivy Bridge]])|| Internal Ring connection, decoded µ-op cache, [[LGA 1155]] socket.
|-
| rowspan = "2" | 2012 || AMD APU A Series ([[Bulldozer (processor)|Bulldozer, Trinity]] and later) || colspan="3" style="background: #ececec;" | 48-bit || [[Advanced Vector Extensions|AVX]], Bulldozer based APU, [[Socket FM2]] or [[Socket FM2+]]
|-
| Intel [[Xeon Phi]] (Knights Corner) || colspan="3" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;"| 48-bit || coprocessor OS powered PCI-E Card Formed coprocessor for XEON based system, Many Core Chip, In-order [[P5 (microarchitecture)|P54C]], very wide VPU (512-bit SSE), LRBni instructions (8× 64-bit)
|-
| rowspan = "3" | 2013. || |AMD [[Jaguar (microarchitecture)|Jaguar]] (Athlon, Sempron) || colspan="3" style="background: #ececec;" | 48-bit|| [[System on a chip|SoC]], game console and low power smart device processor
|-
| Intel [[Silvermont]] (Atom, Celeron, Pentium) ||colspan="3" style="background: #ececec;" | 36-bit|| [[System on a chip|SoC]], low/ultra-low power smart device processor
|-
|[[Intel Core i3]], [[Core i5]] and [[Core i7]] ([[Haswell (microarchitecture)|Haswell]]/[[Broadwell (microarchitecture)|Broadwell]]) || rowspan = "2" colspan="3" style="background: #ececec;" | 39-bit|| [[Advanced Vector Extensions 2|AVX2]], [[FMA instruction set|FMA3]], [[Transactional Synchronization Extensions|TSX]], [[Bit Manipulation Instruction Sets|BMI1, and BMI2]] instructions, [[LGA 1150]] socket
|-
| 2015 || Intel [[Broadwell (microarchitecture)|Broadwell-U]] ([[Intel Core i3]], [[Core i5]], [[Core i7]], [[List of Intel Core M microprocessors|Core M]], [[Pentium]], [[Celeron]]) || SoC, on-chip Broadwell-U PCH-LP (Multi-chip module)
|-
|2015/2016 || Intel [[Skylake (microarchitecture)|Skylake]]/[[Kaby Lake]]/[[Cannon Lake (microarchitecture)|Cannon Lake]] ([[Intel Core i3]], [[Core i5]], [[Core i7]]) || colspan="3" style="background: #ececec;" | 46-bit|| AVX-512 (restricted to Cannon Lake-U and workstation/server variants of Skylake)
|-
| 2016 || Intel [[Xeon Phi]] (Knights Landing) || colspan="3" style="background: #ececec"| 48-bit || Many-core CPU and coprocessor for Xeon systems, Airmont (Atom) core based
|-
|2016 || AMD Bristol Ridge (AMD (Pro) A6/A8/A10/A12) || rowspan="3" colspan="3" style="background: #ececec;" | 48-bit|| Integrated FCH on die, SoC, AM4 socket
|-
|2017 || AMD Ryzen Series/AMD Epyc Series || AMD's implementation of SMT, on-chip multiple dies.
|-
|2017 || Zhaoxin WuDaoKou (KX-5000, KH-20000) || [[Zhaoxin]]'s first brand new x86-64 architecture
|-
|2018/2019 || Intel Sunny Cove (Ice Lake-U and Y) || rowspan="1" colspan="3" style="background: #ececec;" | 57-bit|| Intel's first implementation of AVX-512 for the consumer segment. Addition of Vector Neural Network Instructions
|-
|colspan="2" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;" |Software Emulation [[ARM architecture|ARM64]]||2017||Windows 10 on ARM64||colspan="3"| || Cooperation between Microsoft and Qualcomm bringing Windows 10 onto ARM64 platform with x86 applications supported by CHPE emulator starting from 1709 (16299.15)
|-
!colspan="2"|Era
!Release
!CPU models
!colspan="3"|Physical Address Space
!New features
|}

==Izvori==
{{izvori}}

==Vanjske poveznice==

[[Kategorija: Računarstvo]]

X86 - Povijest promjena

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